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1 of 19 112299 note: some revisions of this device may incorporat e deviations from publishe d specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: http://dbserv.maxim-ic.com/errata.cfm . features 8-bit 8051-compatible microcontroller adapts to task at hand: - 8 or 32 kbytes of nonvolatile ram for program and/or data memory storage - initial downloading of software in end system via on-chip serial port - capable of modifying its own program and/or data memory in end use crashproof operation: - maintains all nonvolatile resources for 10 years in the absence of v cc - power-fail reset - early warning power-fail interrupt - watchdog timer software security feature: - executes encrypted software to prevent unauthorized disclosure on-chip, full-duplex serial i/o ports two on-chip timer/event counters 32 parallel i/o lines compatible with industry standard 8051 instruction set and pinout optional permanently powered real time clock (DS5000T) pin assignment description the ds5000(t) soft microcontroller module is a fully 8051-compatible 8-bit cmos microcontroller that offers ?softness? in all aspects of its application. this is accomplished through the comprehensive use of nonvolatile technology to preserve all info rmation in the absence of system v cc . the internal program/data memory space is implemented using either 8 or 32 kbytes of nonvolatile cmos sram. furthermore, internal data regist ers and key configuration registers are also nonvolatile. an optional real time clock gives permanently powered timekeeping. the clock keeps time to a hundredth of a second using an onboard crystal. DS5000T soft microcontroller module www.maxim-ic.com 1 p1.0 2 p1.1 3 p1.2 4 p1.3 5 p1.4 6 p1.5 7 p1.6 8 p1.7 9 rst 10 rxd p3.0 11 txd p3.1 12 int0 p3.2 13 int1 p3.3 14 t0 p3.4 15 t1 p3.5 16 wr p3.6 17 rd p3.7 18 xtal2 19 xtal1 20 gnd v cc 40 p0.0 ad0 39 p0.1 ad1 38 p0.2 ad2 37 p0.3 ad3 36 p0.4 ad4 35 p0.5 ad5 34 p0.6 ad6 33 p0.7 ad7 32 e a 31 a le 30 psen 29 p2.7 a15 28 p2.6 a14 27 p2.5 a13 26 p2.4 a12 25 p2.3 a11 24 p2.2 a10 23 p2.1 a9 22 p2.0 a8 21 40-pin enca p sulated packa g e
DS5000T 2 of 19 ordering information part number ram size max crystal speed timekeeping? ds5000-8-16 8 kbytes 16 mhz no ds5000-32-16 32 kbytes 16 mhz no ds5000-8-16 8 kbytes 16 mhz yes DS5000T-32-16 32 kbytes 16 mhz yes operating information is contained in the user?s gu ide section of the secure microcontroller data book. this data sheet provides ordering inform ation, pinout, and electrical specifications. ds5000(t) block diagram figure 1
DS5000T 3 of 19 pin description pin description 1-8 p1.0 - p1.7. general purpose i/o port 1. 9 rst - active high reset input. a logic 1 applied to this pin will activate a reset state. this pin is pulled down internally so this pin can be left unconnected if not used. 10 p3.0 rxd. general purpose i/o port pin 3.0. also se rves as the receive signal for the on board uart. this pin should not be c onnected directly to a pc com port. 11 p3.1 txd. general purpose i/o port pin 3.1. also serves as the transmit signal for the on board uart. this pin should not be c onnected directly to a pc com port. 12 p3.2 int0 . general purpose i/o port pin 3.2. also serves as the active low external interrupt 0. 13 p3.3 int1 . general purpose i/o port pin 3.3. also serves as the active low external interrupt 1. 14 p3.4 t0. general purpose i/o port pin 3.4. also serves as the timer 0 input. 15 p3.5 t1. general purpose i/o port pin 3.5. also serves as the timer 1 input. 16 p3.6 wr . general purpose i/o port pin. also serves as the write strobe for expanded bus operation. 17 p3.7 rd . general purpose i/o port pin. also serves as the read strobe for expanded bus operation. 18, 19 xtal2, xtal1. used to connect an external crystal to the internal oscillator. xtal1 is the input to an inverting amplifier and xtal2 is the output. 20 gnd. logic ground. 21-28 p2.0-p2.7. general purpose i/o port 2. also serves as the msb of the expanded address bus. 29 psen - program store enable. this active low signal is used to enable an external program memory when using the expanded bus . it is normally an output and should be unconnected if not used. psen also is used to invoke the bootstrap loader. at this time, psen will be pulled down externally. this should only be done once the ds5000(t) is already in a reset state. the device that pu lls down should be open drain since it must not interfere with psen under normal operation. 30 ale - address latch enable. used to de-multiplex the multiplexed expanded address/data bus on port 0. this pin is nor mally connected to the clock input on a ?373 type transparent latch. when using a parallel programmer, this pin also assumes the prog function for programming pulses. 31 ea - external access. this pin forces the ds 5000(t) to behave like an 8031. no internal memory (or clock) will be available when this pin is at a logic low. since this pin is pulled down internally, it should be connected to +5v to use nv ram. in a parallel programmer, this pin also serves as v pp for super voltage pulses. 32-39 p0.7-p0.0. general purpose i/o port 0. this port is open-drain and cannot drive a logic 1. it requires external pullups. port 0 is also the multiplexed expanded address/data bus. when used in this mode, it does not require pullups. 40 v cc - +5 volts.
DS5000T 4 of 19 instruction set the ds5000(t) executes an instruction set which is object code-compatible with the industry standard 8051 microcontroller. as a result, software developm ent packages which have been written for the 8051 are compatible with the ds5000(t), including cross- assemblers, high-level language compilers, and debugging tools. a complete description for the ds5000(t) instruction se t is available in the user?s guide section of the secure microcontroller data book. memory organization figure 2 illustrates the address spaces which are acc essed by the ds5000(t). as illustrated in the figure, separate address spaces exist for program and data memory. since the basic addressing capability of the machine is 16 bits, a maximum of 64 kbytes of progr am memory and 64 kbytes of data memory can be accessed by the ds5000(t) cpu. the 8- or 32-kbyte ram area inside of the ds5000(t) can be used to contain both program and data memory. the real time clock (rtc) in the DS5000T is reached in the memory map by setting a sfr bit. the mcon.2 bit (ece2) is used to select an alternat e data memory map. while ece2=1, all movxs will be routed to this alternate memory map. the real time clock is a serial device that resides in this area. a full description of the rtc access and example software is given in the user?s guide section of the secure microcontroller data book. if the ece2 bit is set on a ds5000 without a timekeeper, the movxs will simply go to a nonexistent memory. softwa re execution would not be affected otherwise.
DS5000T 5 of 19 ds5000(t) logical address spaces figure 2 program loading the program load modes allow initialization of the nv ram program/data memory. this initialization may be performed in one of two ways: 1. serial program loading which is capable of pe rforming bootstrap loading of the ds5000(t). this feature allows the loading of the application prog ram to be delayed until th e ds5000(t) is installed in the end system. dallas semiconductor strongly r ecommends the use of serial program loading because of its versatility and ease of use. 2. parallel program load cycles which perform the initial loading from parallel address/data information presented on the i/o port pins. this mode is timin g set-compatible with the 8751h microcontroller programming mode. the ds5000(t) is placed in its program load configur ation by simultaneously applying a logic 1 to the rst pin and forcing the psen line to a logic 0 level. immediately following this action, the ds5000(t) will look for a parallel program load pulse, or a serial ascii carriage return (0 dh) character received at 9600, 2400, 1200, or 300 bps over the serial port. the hardware configurations used to select these modes of operation are illustrated in figure 3.
DS5000T 6 of 19 program loading configurations figure 3 table 1 summarizes the selection of the available parallel program load cycles. the timing associated with these cycles is illustrated in the electrical specs. serial bootstrap loader the serial program load mode is the easiest, fa stest, most reliable, a nd most complete method of initially loading application software into the ds5000(t) nonvolatile ra m. communication can be performed over a standard asynch ronous serial communications port. a typical application would use a simple rs232c serial interface to program the ds5000( t) as a final production procedure. the hardware configuration which is required for the serial program load mode is illustrated in figure 3. port pins 2.7 and 2.6 must be either open or pu lled high to avoid placing the ds5000(t) in a parallel load cycle. although an 11.0592 mhz crystal is shown in figure 3, a variety of crystal frequencies and loader baud rates are supported, shown in table 2. the serial loader is designed to operate across a 3-wire interface from a standard uart. the receive, transmit, and gr ound wires are all that are necessary to establish communication with the ds5000(t). the serial bootstrap loader implements an easy-to-use command line interface which allows an application program in an intel hex representation to be loaded into and read back from the device. intel hex is the typical format which existing 8051 cross- assemblers output. the serial loader responds to single character commands which are summarized below:
DS5000T 7 of 19 command function c return crc-16 checksum of embedded ram d dump intel hex file f fill embedded ram block with constant k load 40-bit encryption key l load intel hex file r read mcon register t trace (echo) incoming intel hex data u clear security lock v verify embedded ram with incoming intel hex w write mcon register z set security lock p put a value to a port g get a value from a port parallel program load cycles table 1 mode rst psen prog ea p2.7 p2.6 p2.5 program 1 0 0 v pp 10x security set 1 0 0 v pp 11x verify 1xx100x prog expanded 1 0 0 v pp 010 verify expanded 1 0 1 1 0 1 0 prog mcon or key registers 1 0 0 v pp 011 verify mcon registers 1 0 1 1 0 1 1 the parallel program cycle is used to load a byte of data into a register or memory location within the ds5000(t). the verify cycle is used to read this by te back for comparison with the originally loaded value to verify proper loading. the security set cycle may be used to enable and the software security feature of the ds5000(t). one may also enter bytes for the mcon register or for the five encryption registers using the program mcon cycle. when using this cycle, the absolute register address must be presented at ports 1 and 2 as in the normal prog ram cycle (port 2 should be 00h). the mcon contents can likewise be verified using the verify mcon cycle. when the ds5000(t) first detects a pa rallel program strobe pul se or a security set strobe pulse while in the program load mode following a power-on re set, the internal hardware of the ds5000(t) is initialized so that an existing 4-kbyte program can be programmed into a ds5000(t) with little or no modification. this initialization automatically sets th e range address for 8 kbytes and maps the lowest 4- kbyte bank of embedded ram as program memory. the next 4 kbytes of embedded ram are mapped as data memory. in order to program more than 4 kbytes of prog ram code, the program/verify expanded cycles can be used. up to 32 kbytes of program code can be en tered and verified. note that the expanded 32-kbyte program/ verify cycles take much longer than the normal 4-kbyte program/verify cycles. a typical parallel loading session would follow this procedure. first, set the contents of the mcon register with the correct range and partition only if using expanded programming cycles. next, the encryption registers can be loaded to enable encryption of the program/data memory (not required). then,
DS5000T 8 of 19 program the ds5000(t) using either normal or expanded program cycles and check the memory contents using verify cycles. the last operation would be to turn on the security lock feature by either a security set cycle or by explicitly writing to the mcon register and setting mcon.0 to a 1. serial loader baud rates for different crystal frequencies table 2 baud rate crystal freq (mhz) 300 1200 2400 9600 19200 57600 14.7456 y y y y 11.0592 y y y y y y 9.21600 y y y y 7.37280 y y y y 5.52960 y y y y 1.84320 y y y y additional information a complete description for all ope rational aspects of the ds5000(t), is provided in the user?s guide section of the secure microcontroller data book. development support dallas semiconductor offers a kit package for de veloping and testing user code. the DS5000Tk evaluation kit allows the user to download intel he x formatted code directly to the ds5000(t) from a pc-xt/at or compatible computer. the kit consis ts of a DS5000T-32, an interface pod, demo software, and an rs232 connector that attaches to the com1 or com2 serial port of a pc. see the development tools section of the secure microcont roller data book for further details.
DS5000T 9 of 19 absolute maximum ratings* voltage on any pin relativ e to ground -0.3v to +7.0v operating temperature 0c to 70c storage temperature -40c to +70c soldering temperature 260c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc characteristics (t a =0 c to 70 c; v cc =5v 5%) parameter symbol min typ max units notes input low voltage v il -0.3 0.8 v 1 input high voltage v ih1 2.0 v cc +0.3 v 1 input high voltage rst, xtal1 v ih2 3.5 v cc +0.3 v 1 output low voltage @ i ol =1.6 ma (ports 1, 2, 3) v ol1 0.15 0.45 v output low voltage @ i ol =3.2 ma (ports 0, ale, psen ) v ol2 0.15 0.45 v 1 output high voltage @ i oh =-80 a (ports 1, 2, 3) v oh1 2.4 4.8 v 1 output high voltage @ i oh =-400 a (ports 0, ale, psen ) v oh2 2.4 4.8 v 1 input low current v in = 0.45v (ports 1, 2, 3) i il -50 a transition current; 1 to 0 v in =2.0v (ports 1, 2, 3) i tl -500 a input leakage current 0.45 < v in < v cc (port 0) i l 10 a rst, ea pulldown resistor r re 40 125 k stop mode current i sm 80 a 4 power-fail warning voltage v pfw 4.15 4.6 4.75 v 1 minimum operating voltage v ccmin 4.05 4.5 4.65 v 1 programming supply voltage (parallel program mode) v pp 12.5 13 v 1 program supply current i pp 15 20 ma operating current ds5000-8k @ 8mhz ds5000-32k @ 12 mhz ds5000(t)-32-16 @ 16 mhz i cc 25.2 35.7 45.6 43 48 54 ma 2 idle mode current @ 12 mhz i cc 4.5 6.2 ma 3
DS5000T 10 of 19 ac characteristics: expanded bus mode timing specifications (t a =0 c to 70 c; v cc =5v 5%) # parameter symbol min max units 1 oscillator frequency 1/t clk 1.0 16 mhz 2 ale pulse width t alpw 2t clk -40 ns 3 address valid to ale low t avall t clk -40 ns 4 address hold after ale low t avaav t clk -35 ns 5 ale low to valid instr. in @ 12 mhz @ 16 mhz t allvi 4t clk -150 4t clk -90 ns ns 6 ale low to psen low t allpsl t clk -25 ns 7 psen pulse width t pspw 3t clk -35 ns 8 psen low to valid instr. in @ 12 mhz @ 16 mhz t pslvi 3t clk -150 3t clk -90 ns ns 9 input instr. hold after psen going high t psiv 0ns 10 input instr. float after psen going high t psix t clk -20 ns 11 address hold after psen going high t psav t clk -8 ns 12 address valid to valid instr. in @ 12 mhz @ 16 mhz t avvi 5t clk -150 5t clk -90 ns ns 13 psen low to address float t pslaz 0ns 14 rd pulse width t rdpw 6t clk -100 ns 15 wr pulse width t wrpw 6t clk -100 ns 16 rd low to valid data in @ 12 mhz @ 16 mhz t rdldv 5t clk -165 5t clk -105 ns ns 17 data hold after rd high t rdhdv 0ns 18 data float after rd high t rdhdz 2t clk -70 ns 19 ale low to valid data in @ 12 mhz @ 16 mhz t allvd 8 clk -150 8t clk -90 ns ns 20 valid addr. to valid data in @ 12 mhz @ 16 mhz t avdv 9t clk -165 9t clk -105 ns ns 21 ale low to rd or wr low t allrdl 3t clk -50 3t clk +50 ns 22 address valid to rd or wr low t avrdl 4t clk -130 ns 23 data valid to wr going low t dvwrl t clk -60 ns 24 data valid to wr high @ 12 mhz @ 16 mhz t dvwrh 7t clk -150 7t clk -90 ns ns 25 data valid after wr high t wrhdv t clk -50 ns 26 rd low to address float t rdlaz 0ns 27 rd or wr high to ale high t rdhalh t clk -40 t clk +50 ns
DS5000T 11 of 19 expanded program memory read cycle expanded data memory read cycle
DS5000T 12 of 19 expanded data memory write cycle external clock timing
DS5000T 13 of 19 ac characteristics (cont'd) external clock drive (t a =0 c to 70 c; v cc =5v 5%) # parameter symbol min max units 28 external clock high time @ 12 mhz @ 16 mhz t clkhpw 20 15 ns ns 29 external clock low time @ 12 mhz @ 16 mhz t clklpw 20 15 ns ns 30 external clock rise time @ 12 mhz @ 16 mhz t clkr 20 15 ns ns 31 external clock fall time @ 12 mhz @ 16 mhz t clkf 20 15 ns ns ac characteristics (cont'd) serial port timing - mode 0 (t a =0 c to 70 c; v cc =5v 5%) # parameter symbol min max units 35 serial port cycle time t spclk 12t clk s 36 output data setup to rising clock edge t doch 10t clk -133 ns 37 output data hold after rising clock edge t chdo 2t clk -117 ns 38 clock rising edge to input data valid t chdv 10t clk -133 ns 39 input data hold after rising clock edge t chdiv 0ns serial port timing - mode 0
DS5000T 14 of 19 ac characteristics (cont'd) power cycling timing (t a =0 c to 70 c; v cc =5v 5%) # parameter symbol min max units 32 slew rate from v ccmin to 3.3v t f 40 s 33 crystal start-up time t csu (note 5) 34 power-on reset delay t por 21504 t clk power cycle timing
DS5000T 15 of 19 ac characteristics (cont'd) parallel program load timing (t a =0 c to 70 c; v cc =5v 5%) # parameter symbol min max units 40 oscillator frequency 1/t clk 1.0 12.0 mhz 41 address setup to prog low t avprl 0 42 address hold after prog high t prhav 0 43 data setup to prog low t dvprl 0 44 data hold after prog high t prhdv 0 45 p2.7, 2.6, 2.5 setup to v pp t p27hvp 0 46 v pp setup to prog low t vphprl 0 47 v pp hold after prog low t prhvpl 0 48 prog width low t prw 2400 t clk 49 data output from address valid t avdv 48 1800* t clk 50 data output from p2.7 low t dvp27l 48 1800* t clk 51 data float after p2.7 high t p27hdz 048 1800* t clk 52 delay to reset/ psen active after power on t porpv 21504 t clk 53 reset/ psen active (or verify inactive) to v pp high t ravph 1200 t clk 54 v pp inactive (between program cycles) t vpppc 1200 t clk 55 verify active time t vft 48 2400* t clk * second set of numbers refers to ex panded memory progra mming up to 32k bytes.
DS5000T 16 of 19 parallel program load timing capacitance (test frequency=1mhz; t a =25 c) parameter symbol min typ max units notes output capacitance c o 10 pf input capacitance c i 10 pf
DS5000T 17 of 19 ds5000(t) typical i cc vs. frequency normal operation is measured using: 1) external crystals on xtal1 and 2 2) all port pins disconnected 3) rst=0 volts and ea=v cc 4) part performing endless loop writing to internal memory idle mode operation is measured using: 1) external clock source at xtal1; xtal2 floating 2) all port pins disconnected 3) rst=0 volts and ea=v cc 4) part set in idle mode by software
DS5000T 18 of 19 notes: 1. all voltages are referenced to ground. 2. maximum operating i cc is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10 ns, v il = 0.5v; xtal2 disconnected; ea = rst = port0 = v cc . 3. idle mode i cc is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10 ns, v il = 0.5v; xtal2 disconnected; ea = port0 = v cc , rst = v ss . 4. stop mode i cc is measured with all output pins disconnected; ea = port0 = v cc ; xtal2 not connected; rst = v ss . 5. crystal start-up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. the user should check with the crys tal vendor for the worst case spec on this time. package drawing inches dim min max a in. 2.080 2.100 b in. 0.680 0.700 c in. 0.290 0.325 d in. 0.090 0.110 e in. 0.030 0.060 f in. 0.145 0.185 g in. 0.016 0.020 h in. 0.590 0.610 i in. 0.009 0.015
DS5000T 19 of 19 data sheet revision summary the following represent the key differences be tween the dates 07/20/95 to 07/24/96 of the ds5000(t) data sheet. please review this summary carefully. 1. correct figure 3 to show rst active high. 2. add data sheet revision summary.

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